A system testing multiple undiced integrated circuits (that is, devices under test) formed on a semiconductor wafer at a time or in several batches generally comprises a test stage having a chuck top receiving the devices under test on the upper surface and an electrical connecting apparatus connecting the devices under test to external electrical circuits and arranged over the chuck top.
As one of such electrical connecting apparatuses, there is one comprising a chip unit having a chip supporting body and a plurality of test chips arranged on the upper side of the chip supporting body, a probe unit spaced downward from the chip unit and having a probe supporting body and a plurality of contacts arranged on the lower side of the probe supporting body, and a connecting unit arranged between the chip unit and the probe unit and having a pin supporting body and a plurality of connecting pins penetrating the pin supporting body in the up-down direction and enabling the upper end and the lower end to be protruded upward and downward from the pin supporting body (refer to Japanese Patent Appln. Public Disclosure No. H10-510682 and H11-251383).
In the aforementioned art, each test chip is connected to an external electrical circuit and has a function of generating electrical signals for use in an electrical test of a device under test and receiving and processing response signals from the device under test. Accordingly, with this art, since a plurality of wiring boards on which a plurality of circuits having functions of the test chips are arranged are not needed, the size of a test head is reduced more significantly than required more previously than this art, and a testing system becomes more reasonable.
However, in the aforementioned art, the chip unit, probe unit and connecting unit are just stacked in their thickness dimension. These three units are not coupled to or supported by a supporting unit.